1. Field of the Invention
The present invention relates generally to capacitor structures employed within microelectronic fabrications. More particularly, the present invention relates to methods for forming capacitor structures employed within microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprise a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor stud which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic memory fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, as semiconductor integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to readily form dynamic random access memory (DRAM) cell structures with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may be readily formed, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, dynamic random access memory (DRAM) cell structures.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Prall et al., in U.S. Pat. No. 5,866,453 (a sequential anisotropic etch method and isotropic etch method for forming, with enhanced photolithographic registration tolerance, a bitline stud layer within a capacitor under bitline dynamic random access memory (DRAM) cell structure); and (2) Kotecki et al., in U.S. Pat. No. 6,262,450 (a damascene method for forming, with enhanced efficiency, an at least partially borderless capacitor contact via within a capacitor over bitline dynamic random access memory (DRAM) cell structure).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for readily forming, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.